SN74AHCT240-Q1_V01中文资料德州仪器数据手册PDF规格书

Qualified for Automotive Applications

Inputs Are TTL-Voltage Compatible

Latch-Up Performance Exceeds 250 mA Per

JESD 17

description/ordering information

This octal buffer/driver is designed specifically to

improve the performance and density of 3-state

memory-address drivers, clock drivers, and

bus-oriented receivers and transmitters.

The SN74AHCT240 device is organized as two 4-bit

buffers/line drivers with separate output-enable (OE)

inputs. When OE is low, the device passes data from

the A inputs to the Y outputs. When OE is high, the

outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.