SN74AHCT174数据手册集成电路（IC）的触发器规格书PDF

描述 Description

These positive-edge-triggered D-type flip-flops have a direct clear (CLR)\\ input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

特性 Features

• Inputs Are TTL-Voltage Compatible
• Contain Six Flip-Flops With Single-Rail Outputs
• Applications Include:
• Buffer/Storage Registers
• Shift Registers
• Pattern Generators

• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)