SN74AHCT139DBR.A中文资料德州仪器数据手册PDF规格书

Inputs Are TTL-Voltage Compatible

Designed Specifically for High-Speed

Memory Decoders and Data-Transmission

Systems

Incorporate Two Enable Inputs to Simplify

Cascading and/or Data Reception

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

The ’AHCT139 devices are dual 2-line to 4-line

decoders/demultiplexers designed for 4.5-V to

5.5-V VCC operation. These devices are

designed to be used in high-performance

memory-decoding or data-routing applications

requiring very short propagation delay times. In

high-performance memory systems, these

decoders can be used to minimize the effects of

system decoding. When used with high-speed

memories utilizing a fast enable circuit, the delay

times of these decoders and the enable time of the

memory usually are less than the typical access

time of the memory. This means that the effective

system delay introduced by the decoders is

negligible.