SN74AHC123A集成电路（IC）的多谐振荡器规格书PDF中文资料

SN74AHC123A属于集成电路（IC）的多谐振荡器。由美国德州仪器公司制造生产的SN74AHC123A多谐振荡器多谐振荡器是简单的双态器件，尽管它们的典型使用方式在很大程度上具有模拟特性，但通常被认为是数字逻辑元器件。单稳型也称为“单发”，具有一种稳定状态；但施加触发信号可使它们离开此状态一段时间，该时间通常由所连接电容器的值来确定。这些器件对于去弹跳开关触头等应用非常有用。非稳型没有稳定状态，在两个状态之间按一定频率持续转换，该频率通常也是由所连接电容器的值来确定。

FEATURES

· Controlled Baseline

– One Assembly Site

– One Test Site

– One Fabrication Site

· Extended Temperature Performance of –55°C

to 125°C

· Enhanced Diminishing Manufacturing Sources

(DMS) Support

· Enhanced Product-Change Notification

· Qualification Pedigree (1)

· Operating Range 2-V to 5.5-V VCC

· Schmitt-Trigger Circuitry On A, B, and CLR

Inputs for Slow Input Transition Rates

· Edge Triggered From Active-High or

Active-Low Gated Logic Inputs

· Retriggerable for Long Output Pulses

· Overriding Clear Terminates Output Pulse

· Glitch-Free Power-Up Reset On Outputs

· Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74AHC123A device is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC

operation.

This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the

A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In

the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external

timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected

between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between

Rext/Cext and VCC. The output pulse duration can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input

pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition

rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or

high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or

B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device is less than ±0.5% (typ) for given external timing

components. An example of this distribution for the SN74AHC123A is shown in Figure 10. Variations in output

pulse duration versus supply voltage and temperature are shown in Figure 6.