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SN74ACT7813-15DL.A中文资料德州仪器数据手册PDF规格书

SN74ACT7813-15DL.A
厂商型号

SN74ACT7813-15DL.A

功能描述

64 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

丝印标识

ACT7813-15

封装外壳

SSOP

文件大小

326.06 Kbytes

页面数量

17

生产厂商 Texas Instruments
企业简称

TI2德州仪器

中文名称

美国德州仪器公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-8-2 23:00:00

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SN74ACT7813-15DL.A规格书详情

Member of the Texas Instruments

WidebusE Family

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

Read and Write Operations Synchronized

to Independent System Clocks

Input-Ready Flag Synchronized to Write

Clock

Output-Ready Flag Synchronized to Read

Clock

64 Words by 18 Bits

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width

Expansion Without Additional Logic

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 67 MHz

Pin-to-Pin Compatible With SN74ACT7803

and SN74ACT7805

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

The SN74ACT7813 is a 64-word × 18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and

GND pins, along with Texas Instruments patented output edge control (OECE) circuit, dampen simultaneous

switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless

of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

供应商 型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
24+
SSOP56
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
TI/德州仪器
24+
NA/
3274
原厂直销,现货供应,账期支持!
询价
TI
22+
56-SSOP
5000
全新原装,力挺实单
询价
TI/德州仪器
25+
SSOP-56
860000
明嘉莱只做原装正品现货
询价
TI
2025+
SSOP-56
16000
原装优势绝对有货
询价
TI
24+
5000
自己现货
询价
TI/德州仪器
24+
SSOP-56
9600
原装现货,优势供应,支持实单!
询价
TexasInstruments
18+
ICCLOCKEDFIFOMEMORY56-SS
6800
公司原装现货/欢迎来电咨询!
询价
TI/德州仪器
25+
SSOP-56
9980
只做原装 支持实单
询价
TI
16+
SSOP
10000
原装正品
询价