SN74ACT563PWR.A中文资料德州仪器数据手册PDF规格书

4.5-V to 5.5-V VCC Operation

Inputs Accept Voltages to 5.5 V

Max tpd of 8.5 ns at 5 V

Inputs Are TTL-Voltage Compatible

3-State Inverted Outputs Drive Bus Lines

Directly

Flow-Through Architecture to Optimize

PCB Layout

description/ordering information

The ’ACT563 devices are octal D-type

transparent latches with 3-state outputs. When

the latch-enable (LE) input is high, the Q outputs

are set to the complements of the data (D) inputs.

When LE is taken low, the Q outputs are latched

at the inverse logic levels set up at the D inputs.

A buffered output-enable (OE) input places the

eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and increased high logic

level provide the capability to drive bus lines

without interface or pullup components.

OE does not affect internal operations of the

latches. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.