16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.09 Kbytes 页数：19 Pages

TI

德州仪器

16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：139.34 Kbytes 页数：13 Pages

TI

德州仪器

16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：399.78 Kbytes 页数：15 Pages

TI

德州仪器

具有三态输出的 16 位寄存收发器

The 'ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The 'ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable ( or) and output-enable ( or ) inputs are provided for each • Members of the Texas Instruments WidebusTM Family• State-of-the-Art EPIC-IIBTM BiCMOS DesignSignificantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C• Distributed VCC and GND Pin Configuration Mi;

TI

德州仪器

丝印：ABT16543；Package：TSSOP(DGG)；16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.87 Kbytes 页数：19 Pages

TI

德州仪器

丝印：ABT16543；Package：TSSOP；16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.09 Kbytes 页数：19 Pages

TI

德州仪器

丝印：ABT16543；Package：TSSOP；16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.09 Kbytes 页数：19 Pages

TI

德州仪器

丝印：ABT16543；Package：TSSOP(DGG)；16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.87 Kbytes 页数：19 Pages

TI

德州仪器

丝印：ABT16543；Package：TSSOP(DGG)；16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.87 Kbytes 页数：19 Pages

TI

德州仪器

丝印：ABT16543；Package：TSSOP(DGG)；16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments WidebusE Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：641.87 Kbytes 页数：19 Pages

TI

德州仪器