SN65MLVD128DGGR.B中文资料德州仪器数据手册PDF规格书

FEATURES

· LVTTL Receiver and Eight Line Drivers

Configured as an 8-Port M-LVDS Repeater –

SN65MLVD128

· 2 LVTTL Receivers and Eight Line Drivers

Configured as Dual 4-Port M-LVDS Repeaters

– SN65MLVD129

· Drivers Meet or Exceed the M-LVDS Standard

(TIA/EIA-899)

· Low-Voltage Differential 30-W to 55-W Line

Drivers for Data Rates (1) Up to 250 Mbps or

Clock Frequencies Up to 125 MHz

· Power Up/Down Glitch Free

· Controlled Driver Output Voltage Transition

Times for Improved Signal Quality

Bus Pins High Impedance When Disabled or

VCC £ 1.5 V

Independent Enables for each Driver

Output-to-Ouput Skew tsk(o) £ 160 ps

Part-to-Part Skew tsk(pp) £ 800 ps

Single 3.3-V Voltage Supply

Bus Pin ESD Protection Exceeds 9 kV

Packaged in 48-Pin TSSOP (DGG)

APPLICATIONS

AdvancedTCA™ (ATCA™) Clock Bus Driver

Clock Distribution

Data and Clock Repeating Over Backplanes

and Cables

Cellular Base Stations

Central Office Switches

Network Switches and Routers

DESCRIPTION

The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M-LVDS translators/repeaters. Outputs comply with the

M-LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to

125 MHz. The driver outputs have been designed to support multipoint buses presenting loads as low as 30 W

and incorporates controlled transition times for backbone operation.

M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for

RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The

SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each

output signal.

Intended applications for these devices include transmission of clock signals from a central clock module, as well

as translation and buffering of data or control signals for transmission through a controlled impedance backplane

or cable.