SN65LVP19DRFT集成电路（IC）的信号缓冲器、中继器、分离器规格书PDF中文资料

SN65LVP19DRFT属于集成电路（IC）的信号缓冲器、中继器、分离器。由德州仪器制造生产的SN65LVP19DRFT信号缓冲器、中继器、分离器信号缓冲器、中继器和分离器系列中的产品适用于远距离电气互连或电缆系统的数字信息传输。所有实际互连系统都具有非理想特性，该系列产品主要用于解决数字信息传输过程中因此造成的模拟问题。此外，还有其他功能，例如不同物理接口样式之间的转换和多路复用。

FEATURES

· Low-Voltage PECL Input and Low-Voltage

PECL or LVDS Outputs

· Clock Rates to 1 GHz

– 250-ps Output Transition Times

– 0.12 ps Typical Intrinsic Phase Jitter

– Less than 630 ps Propagation Delay Times

· 2.5-V or 3.3-V Supply Operation

· 2-mm x 2-mm Small-Outline

No-Lead Package

APPLICATIONS

· PECL-to-LVDS Translation

· Clock Signal Amplification

DESCRIPTION

These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain

outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on

the SN65LVx18) and fully differential inputs on the SN65LVx19.

The SN65LVx18 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV

either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The

Q on the SN65LVx19 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended

PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.