3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

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德州仪器

3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

文件：271.19 Kbytes 页数：10 Pages

TI

德州仪器

3.3V 双路差动 LVPECL 缓冲器至 LVTTL 转换器

The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open.The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.\n • Dual 3.3-VDifferential LVPECL/LVDS to LVTTL Buffer Translator\n• Operating Range \n• Support for Clock Frequenciesto >180 MHz\n• Internal Input Pullup and Pulldown Resistors\n• Drop-In Compatible to MC100LVELT23\n• Signaling Level Conversion for Clock or Data;

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.66 Kbytes 页数：18 Pages

TI

德州仪器

丝印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：SIMI；Package：VSSOP(DGK)；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.66 Kbytes 页数：18 Pages

TI

德州仪器

丝印：SIMI；Package：MSOP；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：SIMI；Package：VSSOP；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.26 Kbytes 页数：18 Pages

TI

德州仪器

丝印：SIMI；Package：VSSOP(DGK)；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES · Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator · 24-mA LVTTL Ouputs · Operating Range – PECL VCC = 3 V to 3.6 V With GND = 0 V · Support for Clock Frequencies to >180 MHz · 2-ns Typical Propagation Delay · Internal Input Pullup and Pulldown Resistors · Built-i

文件：555.66 Kbytes 页数：18 Pages

TI

德州仪器