LVDS SERDES TRANSMITTER

1FEATURES • 3:21 Data Channel Compression at up to 1.428 Gigabits/s Throughput • Suited for Point-to-Point Subsystem Communication With Very Low EMI • 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential • Operates From a Single 3.3-V S

文件：445.27 Kbytes 页数：22 Pages

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德州仪器

LVDS SERDES TRANSMITTER

Qualified for Automotive Applications 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 21 Data Channels Plus Clock in Low-Voltage TTL and 3 Data Channels Plus Clock Out Low-Voltage Differential Op

文件：462.36 Kbytes 页数：18 Pages

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德州仪器

LVDS SERDES TRANSMITTER

文件：364.51 Kbytes 页数：15 Pages

TI

德州仪器

增强型产品 LVDS 串行器/解串器变送器

The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL • Controlled Baseline \n• Enhanced Diminishing Manufacturing Sources (DMS) Support\n• Qualification Pedigree\n• Suited for Point-to-Point Subsystem Communication With Very Low EMI\n• Operates From a Single 3.3-V Supply and 250 mW (Typ)\n• ’LVDS95 Has Rising Clock Edge Triggered Inputs\n• Packaged in;

TI

德州仪器