SN65LVDS33PW.B中文资料德州仪器数据手册PDF规格书

1FEATURES

• 400-Mbps Signaling Rate(1) and 200-Mxfr/s

Data Transfer Rate

• Operates With a Single 3.3-V Supply

• -4 V to 5 V Common-Mode Input Voltage

Range

• Differential Input Thresholds <±50 mV With 50

mV of Hysteresis Over Entire Common-Mode

Input Voltage Range

• Integrated 110-Ω Line Termination Resistors

On LVDT Products

• TSSOP Packaging (33 Only)

• Complies With TIA/EIA-644 (LVDS)

• Active Failsafe Assures a High-Level Output

With No Input

• Bus-Pin ESD Protection Exceeds 15 kV HBM

• Input Remains High-Impedance on Power

Down

• TTL Inputs Are 5 V Tolerant

• Pin-Compatible With the AM26LS32,

SN65LVDS32B, μA9637, SN65LVDS9637B

DESCRIPTION

This family of four LVDS data line receivers offers the

widest common-mode input voltage range in the

industry. These receivers provide an input voltage

range specification compatible with a 5-V PECL

signal as well as an overall increased ground-noise

tolerance. They are in industry standard footprints

with integrated termination as an option.

Precise control of the differential input voltage

thresholds allows for inclusion of 50 mV of input

voltage hysteresis to improve noise rejection on

slowly changing input signals. The input thresholds

are still no more than ±50 mV over the full input

common-mode voltage range.

The high-speed switching of LVDS signals usually

necessitates the use of a line impedance matching

resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of

receivers eliminates this external resistor by

integrating it with the receiver. The nonterminated

SN65LVDS series is also available for multidrop or

other termination circuits.