PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

文件：1.27586 Mbytes 页数：31 Pages

TI

德州仪器

QVGA-HVGA 27-Bit Display Serial Interface Receiver

The SN65LVDS306 receiver deserializes FlatLink™3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS306 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the p • Serial Interface Technology\n• Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over One SubLVDS Differential Line \n• Up to 405-Mbps Data Throughput\n• Typical Shutdown: 0.7 µW \n• Bus-Swap Function for PCB-Layout Flexibility\n• Pixel Clock Range of 4 MHz-15 MHz\n• Pa;

TI

德州仪器

PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

文件：1.27586 Mbytes 页数：31 Pages

TI

德州仪器

Package：80-VFBGA；包装：卷带（TR） 类别：集成电路（IC） 驱动器，接收器，收发器 描述：IC RECEIVER 0/1 80BGA

TI

德州仪器