SN65LVDS20DRFR集成电路（IC）的信号缓冲器、中继器、分离器规格书PDF中文资料

SN65LVDS20DRFR属于集成电路（IC）的信号缓冲器、中继器、分离器。由德州仪器制造生产的SN65LVDS20DRFR信号缓冲器、中继器、分离器信号缓冲器、中继器和分离器系列中的产品适用于远距离电气互连或电缆系统的数字信息传输。所有实际互连系统都具有非理想特性，该系列产品主要用于解决数字信息传输过程中因此造成的模拟问题。此外，还有其他功能，例如不同物理接口样式之间的转换和多路复用。

FEATURES

· Low-Voltage PECL Input and Low-Voltage

PECL or LVDS Outputs

· Signaling Rates to 4 Gbps or Clock Rates

to 2 GHz

– 120-ps Output Transition Times

– Less than 45 ps Total Jitter

– Less than 630 ps Propagation Delay Times

· 2.5-V or 3.3-V Supply Operation

· 2-mm x 2-mm Small-Outline

No-Lead Package

APPLICATIONS

· PECL-to-LVDS Translation

· Data or Clock Signal Amplification

DESCRIPTION

The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater.

The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and

repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low

radiated emissions and minimal added jitter.

The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the

SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A

high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential

transmission lines with nominally 100-W characteristic impedance.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended

PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.