SN65LVDS151DAR.B中文资料德州仪器数据手册PDF规格书

FEATURES

· A Member of the MuxIt™

Serializer-Deserializer Building-Block Chip

Family

· Supports Serialization of up to 10 Bits of

Parallel Data Input at Rates up to 200 Mbps

· PLL Lock/Valid Input Provided to Enable Link

Data Transfers

· Cascadable With Additional SN65LVDS151

MuxIt Serializer-Transmitters for Wider

Parallel Input Data Channel Widths

· LVDS Compatible Differential Inputs and

Outputs Meet or Exceed the Requirements of

ANSI TIA/EIA-644-A

· LVDS Inputs and Outputs ESD Protection

Exceeds 12 kV HBM

· LVTTL Compatible Inputs for Lock/Valid,

Enables, and Parallel Data Inputs Are 5-V

Tolerant

· Operates With 3.3 V Supply

· Packaged in 32-Pin DA Thin Shrink

Small-Outline Package With 26 Mil Terminal

Pitch

DESCRIPTION

MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and

deserializers. The system allows for wide parallel data to be transmitted through a reduced number of

transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)

data interface. The number of bits multiplexed per transmission line is user-selectable and allows for higher

transmission efficiencies than with existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A) low

voltage differential signaling technology for communications between the data source and data destination.

The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase

locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152

receiver-deserializer.

The SN65LVDS151 consists of a 10-bit parallel-in/serial-out shift register, three LVDS differential transmission

line receivers, a pair of LVDS differential transmission line drivers, plus associated input buffers. It accepts up to

10 bits of user data on parallel data inputs (DI-0 ® DI-9) and serializes (multiplexes) the data for transmission

over an LVDS transmission line link. Two or more SN65LVDS151 units may be connected in series (cascaded)

to accommodate wider parallel data paths for higher serialization values. Data is transmitted over the LVDS

serial link at M times the input parallel data clock frequency. The multiplexing ratio M, or number of bits per data

clock cycle, is programmed on the companion SN65LVDS150 MuxIt programmable PLL frequency multiplier with

configuration pins (M1 ® M5). The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt

programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCRI

and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.