SN65LVDS116DGG集成电路（IC）的信号缓冲器、中继器、分离器规格书PDF中文资料

FEATURES

· One Receiver and Sixteen Line Drivers Meet

or Exceed the Requirements of ANSI

EIA/TIA-644 Standard

· Typical Data Signaling Rates to 400 Mbps or

Clock Frequencies to 400 MHz

· Enabling Logic Allows Separate Control of

Each Bank of Four Channels or 2-Bit

Selection of Any One of the Four Banks

· Low-Voltage Differential Signaling With

Typical Output Voltage of 350 mV and a 100-W

Load

· Electrically Compatible With LVDS, PECL,

LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,

SSTL, or HSTL Outputs With External

Termination Networks

· Propagation Delay Times < 4.7 ns

· Output Skew Is < 300 ps and Part-to-Part

Skew < 1.5 ns

· Total Power Dissipation Typically 470 mW

With All Ports Enabled and at 200 MHz

· Driver Outputs or Receiver Input Is High

Impedance When Disabled or With VCC < 1.5

V

· Bus-Pin ESD Protection Exceeds 12 kV

· Packaged in Thin Shrink Small-Outline

Package With 20-Mil Terminal Pitch

DESCRIPTION

The SN65LVDS116 is one differential line receiver

connected to sixteen differential line drivers that

implement the electrical characteristics of low-voltage

differential signaling (LVDS). LVDS, as specified in

EIA/TIA-644, is a data signaling technique that offers

the low-power, low-noise coupling, and fast switching

speeds to transmit data at relatively long distances.

(Note: The ultimate rate and distance of data transfer

is dependent upon the attenuation characteristics of

the media, the noise coupling to the environment, and

other system characteristics.)

The intended application of this device and signaling

technique is for point-to-point or multidrop baseband

data transmission over controlled impedance media of approximately 100 W. The transmission media may

be printed-circuit board traces, backplanes, or cables.

The large number of drivers integrated into the same

substrate along with the low pulse skew of balanced

signaling, allows extremely precise timing alignment

of the signals repeated from the input. This is

particularly advantageous in system clock distribution.

The SN65LVDS116 is characterised for operation

from –40°C to 85°C.