MuxIt™ RECEIVER-DESERIALIZER

1FEATURES 2• A Member of the MuxIt™ Serializer- Deserializer Building-Block Chip Family • Supports Deserialization of One Serial Link Data Channel Input at Rates up to 200 Mbps • PLL Lock/Valid Input Provided to Enable Parallel Data and Clock Outputs • Cascadable With Additional SN65LVDS152

文件：239.32 Kbytes 页数：18 Pages

TI

德州仪器

丝印：65LVDS152；Package：TSSOP；MuxIt™ RECEIVER-DESERIALIZER

1FEATURES 2• A Member of the MuxIt™ Serializer- Deserializer Building-Block Chip Family • Supports Deserialization of One Serial Link Data Channel Input at Rates up to 200 Mbps • PLL Lock/Valid Input Provided to Enable Parallel Data and Clock Outputs • Cascadable With Additional SN65LVDS152

文件：239.32 Kbytes 页数：18 Pages

TI

德州仪器

丝印：65LVDS152；Package：TSSOP；MuxIt™ RECEIVER-DESERIALIZER

1FEATURES 2• A Member of the MuxIt™ Serializer- Deserializer Building-Block Chip Family • Supports Deserialization of One Serial Link Data Channel Input at Rates up to 200 Mbps • PLL Lock/Valid Input Provided to Enable Parallel Data and Clock Outputs • Cascadable With Additional SN65LVDS152

文件：239.32 Kbytes 页数：18 Pages

TI

德州仪器

丝印：65LVDS152；Package：TSSOP；MuxIt™ RECEIVER-DESERIALIZER

1FEATURES 2• A Member of the MuxIt™ Serializer- Deserializer Building-Block Chip Family • Supports Deserialization of One Serial Link Data Channel Input at Rates up to 200 Mbps • PLL Lock/Valid Input Provided to Enable Parallel Data and Clock Outputs • Cascadable With Additional SN65LVDS152

文件：239.32 Kbytes 页数：18 Pages

TI

德州仪器

丝印：65LVDS152；Package：TSSOP；MuxIt™ RECEIVER-DESERIALIZER

1FEATURES 2• A Member of the MuxIt™ Serializer- Deserializer Building-Block Chip Family • Supports Deserialization of One Serial Link Data Channel Input at Rates up to 200 Mbps • PLL Lock/Valid Input Provided to Enable Parallel Data and Clock Outputs • Cascadable With Additional SN65LVDS152

文件：239.32 Kbytes 页数：18 Pages

TI

德州仪器

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 2 GHz – 140-ps Output Transition Times – 0.11 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm × 2-mm Small-Outline No-Lead Package

文件：413.89 Kbytes 页数：18 Pages

TI

德州仪器

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 2 GHz – 140-ps Output Transition Times – 0.11 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm × 2-mm Small-Outline No-Lead Package

文件：413.89 Kbytes 页数：18 Pages

TI

德州仪器

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 2 GHz – 140-ps Output Transition Times – 0.11 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm × 2-mm Small-Outline No-Lead Package

文件：413.89 Kbytes 页数：18 Pages

TI

德州仪器

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 2 GHz – 140-ps Output Transition Times – 0.11 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm × 2-mm Small-Outline No-Lead Package

文件：413.89 Kbytes 页数：18 Pages

TI

德州仪器

2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS

FEATURES · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs · Clock Rates to 2 GHz – 140-ps Output Transition Times – 0.11 ps Typical Intrinsic Phase Jitter – Less than 630 ps Propagation Delay Times · 2.5-V or 3.3-V Supply Operation · 2-mm × 2-mm Small-Outline No-Lead Package

文件：413.89 Kbytes 页数：18 Pages

TI

德州仪器