SN65LBC176A-EP数据手册TI中文资料规格书

描述 Description

The SN65LBC176A-EP differential bus transceiver is a monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. The SN65LBC176A-EP is designed for balanced transmission lines and is compatible with ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC176A-EP offers improved switching performance over its predecessors without sacrificing significantly more power.

The SN65LBC176A-EP combines a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Low device supply current can be achieved by disabling the driver and the receiver.

特性 Features

• Controlled Baseline
• One Assembly/Test Site, One Fabrication Site

• Extended Temperature Performance of –40°C to 125°C
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product Change Notification
• Qualification Pedigree
• High-Speed Low-Power LinBiCMOS™ Circuitry Designed for Signaling Rates Up to 30 Mbps
• Bus-Pin ESD Protection Exceeds 12-kV HBM
• Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987(E)
• Low Skew
• Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments
• Low Disabled Supply Current Requirements . . . 700 µA Maximum
• Common Mode Voltage Range of –7 V to 12 V
• Thermal-Shutdown Protection
• Driver Positive and Negative Current Limiting
• Open-Circuit Fail-Safe Receiver Design
• Receiver Input Sensitivity ...±200 mV Max
• Receiver Input Hysteresis . . . 50 mV Typ
• Glitch-Free Power-Up and Power-Down Protection
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device. LinBiCMOS and LinASIC are trademarks of Texas Instruments.