SN65ELT23DGKG4.B中文资料德州仪器数据手册PDF规格书

1FEATURES

· Dual 5-V Differential PECL-to-TTL Buffer

· 24-mA TTL Ouputs

· Operating Range

– PECL VCC = 4.75 V to 5.25 V with

GND = 0 V

· Support for Clock Frequencies of 250 MHz

(TYP)

· 3.5-ns Typical Propagation Delay

· Output Default Low with Inputs Left Open or

<1.3 V

· Internal Input 50-kΩ Pull-Down Resistor

· Built-In Temperature Compensation

· Drop-In Compatible to the MC100ELT23

APPLICATIONS

· Data and Clock Transmission Over Backplane

· Signaling Level Conversion for Clock or Data

DESCRIPTION

The SN65ELT23 is a low power dual PECL-to-TTL

translator device. The device includes circuitry to

maintain a known logic low level when inputs are in

an open condition. The SN65ELT23 is housed in an

industry standard SOIC-8 package and is also

available in an optional TSSOP-8 package.