SN54SLC8T245PWTSEP中文资料德州仪器数据手册PDF规格书

1 Features

• VID V62/22604

• Radiation tolerant:

– Single event latch-up (SEL) immune up to 43

MeV-cm2 /mg at 125°C

– Total ionizing dose (TID) Radiation Lot

Acceptance Testing (RLAT) for every wafer lot

up to 20 krad(Si)

• Qualified, fully configurable dual-rail design allows

each port to operate with a power supply range

from 0.65 V to 3.6 V

• Operating temperature from –55°C to +125°C

• Multiple direction-control pins allows simultaneous

up and down translation

• Up to 380 Mbps support when translating from 1.8

V to 3.3 V

• VCC isolation feature that effectively isolates both

buses in a power-down scenario

• Partial power-down mode to limit backflow current

in a power-down scenario

• Latch-up performance exceeds 100 mA per JESD

78, class II

• ESD protection exceeds JESD 22

– 8000-V human-body model

– 1000-V charged-device model

2 Applications

• Supports low earth orbit (LEO) space applications

• Space radar and communications

• Space satellite payloads

3 Description

The SN54SLC8T245-SEP device is an 8-bit noninverting

bus transceiver that resolves voltage level

mismatch between devices operating at the latest

voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices

operating at industry standard voltage nodes (1.8 V,

2.5 V, and 3.3 V).

The device operates by using two independent powersupply

rails (VCCA and VCCB) that operate as low as

0.65 V. Data pins A1 through A8 are designed to track

VCCA, which accepts any supply voltage from 0.65 V

to 3.6 V. Data pins B1 through B8 are designed to

track VCCB, which accepts any supply voltage from

0.65 V to 3.6 V.

The SN54SLC8T245-SEP device is designed for

asynchronous communication between data buses.

The device transmits data from the A bus to the B bus

or from the B bus to the A bus, depending on the logic

level of the direction-control inputs (DIR1 and DIR2).

The output-enable (OE) input is used to disable the

outputs so the buses are effectively isolated.

The SN54SLC8T245-SEP device is designed so the

control pins (DIR and OE) are referenced to VCCA.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables

the outputs when the device is powered down.

This inhibits current backflow into the device which

prevents damage to the device.

The VCC isolation feature ensures that if either VCC

input supply is below 100 mV, all level shifter outputs

are disabled and placed into a high-impedance state.

To ensure the high-impedance state of the level shifter

I/Os during power up or power down, OE should be

tied to VCCA through a pullup resistor; the minimum

value of the resistor is determined by the currentsinking

capability of the driver.