丝印：SN54S280J；Package：CDIP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

文件：895.28 Kbytes 页数：21 Pages

TI

德州仪器

丝印：SN54S280J；Package：CDIP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

文件：895.28 Kbytes 页数：21 Pages

TI

德州仪器

丝印：SN54S280J；Package：CDIP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

文件：895.28 Kbytes 页数：21 Pages

TI

德州仪器

丝印：SN54S280J；Package：CDIP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

文件：895.28 Kbytes 页数：21 Pages

TI

德州仪器

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：227.77 Kbytes 页数：6 Pages

TI

德州仪器

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：899.48 Kbytes 页数：24 Pages

TI

德州仪器

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

文件：901.09 Kbytes 页数：17 Pages

TI

德州仪器