SN54LVTH245A-SP数据手册TI中文资料规格书

描述 Description

These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between data buses. They transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\\ input can be used to disable the devices so the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

特性 Features

• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Typical VOLP (Output Ground Bounce)    CC = 3.3 V, TA = 25°C
• Support Unregulated Battery Operation Down to 2.7 V
• Ioff and Power-Up 3-State Support Hot Insertion
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 500 mA Per JESD 17
• ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)