SN54LVC138A数据手册TI中文资料规格书

描述 Description

The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

特性 Features

• Operate From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.8 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) CC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
• Latch-Up Performance Exceeds 250 mA Per JESD 17