SN54LS390J中文资料安森美半导体数据手册PDF规格书

The SN54/74LS390 and SN54/74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input for each section. The two sections can be connected to count in the 8.4.2.1 BCD code or they can count in a biquinary sequence to provide a square wave (50 duty cycle) at the final output.

Each half of the LS393 operates as a Modulo-16 binary divider, with the last three stages triggered in a ripple fashion. In both the LS390 and the LS393, the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.

Each half of each circuit type has a Master Reset input which responds to a HIGH signal by forcing all four outputs to the LOW state.

• Dual Versions of LS290 and LS293

• LS390 has Separate Clocks Allowing ÷2, ÷2.5, ÷5

• Individual Asynchronous Clear for Each Counter

• Typical Max Count Frequency of 50 MHz

• Input Clamp Diodes Minimize High Speed Termination Effects