OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

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德州仪器

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：1.43118 Mbytes 页数：30 Pages

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德州仪器

具有三态输出的八路 D 类透明锁存器

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package\n• 3-State Bus-Driving Outputs\n• Full Parallel Access for Loading\n• Buffered Control Inputs\n• Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)\n• P-N-P Inputs Reduce DC Loading on Data Lines (’S;

TI

德州仪器

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes 页数：24 Pages

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德州仪器

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：331.48 Kbytes 页数：24 Pages

TI

德州仪器

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

文件：694.69 Kbytes 页数：28 Pages

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德州仪器