SN54LS323数据手册TI中文资料规格书

描述 Description

These Low-Power Schottky eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. The clear function is synchronous, and a low level at the clear input clears the register on the next low-to-high transition of the clock.  

特性 Features

• Multiplexed Inputs/Outputs Provide Improved Bit Density
• Four Modes of Operation:
• Hold (Store)
• Shift Left
• Shift Right
• Load Data
• Operates with Outputs Enabled or at High Z
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N-Bit Word Lengths
• Typical Power Dissipation … 175 mW
• Exceptionally Stable Shift (Clock) Frequency … 25 MHz
• Applications:
• Stacked or Push-Down Registers,
• Buffer Storage, and
• Accumulator Registers
• SN54LS299 and SN74LS299 Are Similar But Have Direct Overriding Clear