SN54LS280J中文资料德州仪器数据手册PDF规格书

Generates Either Odd or Even Parity

for Nine Data Lines

Cascadable for n-Bits

Can Be Used to Upgrade Existing

Systems using MSI Parity Circuits

Typical Data-to-Output Delay of Only 14 ns

for “S280 and 33 ns for ‘LS280

Typical Power Dissipation:

‘LS280. ..80 mW

‘S280. . . 335 mW

description

‘These universal, monoltic nine-bit parity generators checkers utize Schottky-clamped TTL high-performance circuitry and

feature odd even outputs to aclate operation of sithr od or even priy pplication. The word-Jength capably is ssi ex.

panded by cascading 25 shown under typical application cata,

‘Series 54LS/74LS and Series 545/743 parity generators checkers offer the designer a trade-off batwean reduced power

‘consumption and high performance. Thess devices can be used to upgrade the performance of most systems utizing the

180 party generator/checker. Although the S280 and 5280 aro plement without expander inputs, th corresponding

function s provided bythe avalabilty of an input a pin 4 and he absence of any internal connection at pin 3. This permit the

15280 and ‘S280 to be substituted or the ‘180 in exising designs to produce an identical function even if L5280's and.

5280's are mixed with existing 180's.

These devices are full compatible with most other TTL circuit. All'LS280 and ‘S280 inputs are buffered to lower the drive

requirements to one Series 54LS/74LS or Sores 545/745 standard oad, respectively.