SN54LS156数据手册TI中文资料规格书

描述 Description

These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.  

特性 Features

• Applications:
• Dual 2-to 4-Line Decoder
• Dual 1-to 4-Line Demultiplexer
• 3-to 8-Line Decoder
• 1-to 8-Line Demultiplexer

• Individual Strobes Simplify Cascading for Decoding or Demultiplexing Larger Words
• Input Clamping Diodes Simplify System Design
• Choice of Outputs:
• Totem Pole ('155, 'LS155A)
• Open-Collector ('156, 'LS156)