SN54LS137J中文资料德州仪器数据手册PDF规格书

Combines Decoder and 3-Bit Address Latch

Incorporates 2 Enable Inputs to Simplify

Cascading

Low Power Dissipation . . . 656 mW Typ

description

The ‘'LS137 is a three-line to eight-line

decoder/demultiplexer with latches on the three ad-

dress inputs. When the latch-enable input (GL) is low,

the LS137 acts as a decoder/demultiplexer. When GL

goes from low to high, the address present at the select

inputs (A,B, and C) is stored in the latches. Further ad-

dress changes are ignored as long as GL remains high.

The output enable controls, G1 and G2, control the

state of the outputs independently of the select or latch-

enable inputs. All of the outputs are high unless G1 is

high and G2 is low. The ‘LS137 is ideally suited for

implementing glitch-free decoders in strobed (stored-

address) applications in bus-oriented systems.