SN54HC195J中文资料德州仪器数据手册PDF规格书

1FEATURES

· Synchronous Parallel Load

· Positive-Edge-Triggered Clocking

· J and K Inputs to First Stage

· Complementary Outputs From Last Stage

· Package Options: Plastic and Ceramic DIPS

and Ceramic Chip Carriers

· Dependable Texas lnstruments Quality and

Reliability

DESCRIPTION/ORDERING INFORMATION

These 4-bit registers feature parallel inputs, parallel

outputs, J-K serial inputs, shift/load control input, and

a direct overriding clear. The registers have two

modes of operation: parallel (broadside) load, and

shift (in the direction QA and QD).

Parallel loading is accomplished by applying the

4-bits of data and taking the shift/load control input

low. The data is loaded into the associated flip-flop

and appears at the outputs after the positive

transition of the clock input. During loading, serial

data flow is inhibited.

Shifting is accomplished synchronously when the

shift/load control input is high. Serial data for this

mode is entered at the J-K inputs. These inputs

permit the first stage to perform as a J-K, D, or T type

flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over

the full military temperature range of –55°C to 125°C.