8 位并行输出串行移位寄存器

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK • Wide Operating Voltage Range of 2 V to 6 V\n• Outputs Can Drive Up to 10 LSTTL Loads\n• Low Power Consumption, 80-µA Maximum ICC\n• Typical tpd = 20 ns\n• ±4-mA Output Drive at 5 V\n• Low Input Current of 1-µA Maximum\n• AND-Gated (Enable/Disable) Serial Inputs\n• Fully Buffered Clock and Serial I;

TI

德州仪器

8-Bit Parallel-Out Serial Shift Registers

文件：1.21398 Mbytes 页数：33 Pages

TI

德州仪器

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

文件：109.25 Kbytes 页数：14 Pages

TI

德州仪器

8-Bit Parallel-Out Serial Shift Registers

文件：1.21398 Mbytes 页数：33 Pages

TI

德州仪器

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

文件：349.57 Kbytes 页数：14 Pages

TI

德州仪器