SN54HC139-SP数据手册TI中文资料规格书

描述 Description

The ’HC139 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The ’HC139 devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G\\) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

特性 Features

• Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
• Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80-µA Max ICC
• Typical tpd = 10 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 µA Max
• Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception