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SN54ALS191A中文资料同步 4 位加/减二进制计数器数据手册TI规格书
SN54ALS191A规格书详情
描述 Description
The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count enable () input is low. A high at inhibits counting. The direction of the count is determined by the level of the down/up (D/U\\) input. When D/U\\ is low, the counter counts up, and when D/U\\ is high, the counter counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs ( and D/U\\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
CLK, D/U\\, and are buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words.
Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output () produces a low-level output pulse under those same conditions, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count (MAX/MIN) output can be used to accomplish look ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C.
特性 Features
• Single Down/Up Count-Control Line
• Look-Ahead Circuitry Enhances Speed of Cascaded Counters
• Fully Synchronous in Count Modes
• Asynchronously Presettable With Load Control
• Package Options Include Plastic Small-Outline (D) Packages,Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic(J) 300-mil DIPs
技术参数
- 制造商编号
:SN54ALS191A
- 生产厂家
:TI
- VCC(Min)(V)
:4.5
- VCC(Max)(V)
:5.5
- Bits(#)
:4
- Voltage(Nom)(V)
:5
- F @ nom voltage(Max)(MHz)
:75
- ICC @ nom voltage(Max)(mA)
:22
- tpd @ nom Voltage(Max)(ns)
:31
- IOL(Max)(mA)
:8
- IOH(Max)(mA)
:-0.4
- Function
:Counter
- Type
:Binary
- Rating
:Military
- Operating temperature range(C)
:-55 to 125
- Package Group
:CDIP|16CFP|16LCCC|20
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI/德州仪器 |
23+ |
CDIP |
11200 |
原厂授权一级代理、全球订货优势渠道、可提供一站式BO |
询价 | ||
24+ |
N/A |
64000 |
一级代理-主营优势-实惠价格-不悔选择 |
询价 | |||
TI/德州仪器 |
2447 |
CDIP |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
TI |
23+ |
DIP |
8000 |
只做原装现货 |
询价 | ||
Rochester |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
询价 | ||
TI |
2021+ |
60000 |
原装现货,欢迎询价 |
询价 | |||
24+ |
25 |
本站现库存 |
询价 | ||||
TI(德州仪器) |
23+ |
15000 |
专业帮助客户找货 配单,诚信可靠! |
询价 | |||
原厂 |
NA |
8650 |
一级代理 原装正品假一罚十价格优势长期供货 |
询价 | |||
TI |
25+ |
金封 |
18000 |
原厂直接发货进口原装 |
询价 |