SN54ACT3632HFP集成电路（IC）的FIFO存储器规格书PDF中文资料

SN54ACT3632HFP属于集成电路（IC）的FIFO存储器。由德州仪器制造生产的SN54ACT3632HFPFIFO 存储器先入先出 (FIFO) 存储器可用于数字信息的短期存储，其中信息检索顺序和序列与信息存储顺序和序列相同。这类产品又称为队列或缓冲存储器，通常用于在单独的设备之间交换信息，尤其是在数据以不同的速率或在略微不同的时间点生成和使用的情况下。

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

Two Independent 512 × 36 Clocked FIFOs

Buffering Data in Opposite Directions

Mailbox-Bypass Register for Each FIFO

Programmable Almost-Full and

Almost-Empty Flags

Microprocessor Interface Control Logic

IRA, ORA, AEA, and AFA Flags

Synchronized by CLKA

Released as DESC SMD (Standard

Microcircuit Drawing) 5962-9562801QYA

IRB, ORB, AEB, and AFB Flags

Synchronized by CLKB

Low-Power 0.8-mm Advanced CMOS

Technology

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 13 ns

Packaged in 132-Pin Ceramic Quad Flat

Package

description

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock

frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port

SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full

conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of

words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox

registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can

be used in parallel to create wider data paths.

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for

each port are independent of one another and can be asynchronous or coincident. The enables for each port

are arranged to provide a simple bidirectional interface between microprocessors and/or buses with

synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the

port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag

of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the

almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN54ACT3632 is characterized for operation over the full military temperature range of –55°C to 125°C.

For more information on this device family, see the following application reports:

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005)

Metastability Performance of Clocked FIFOs (literature number SCZA004)