36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

Members of the Texas Instruments Widebus+E Family State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：292.43 Kbytes 页数：14 Pages

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德州仪器

36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：135.24 Kbytes 页数：9 Pages

TI

德州仪器

36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：201.08 Kbytes 页数：11 Pages

TI

德州仪器

具有三态输出的 36 位寄存总线收发器

The 'ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB\\ or LEBA\\) and output-enable (OEAB\\ or O • Members of the Texas InstrumentsWidebus+TM Family• State-of-the-ArtEPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C• High-Impedance State During Power Up and Po;

TI

德州仪器

36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：201.08 Kbytes 页数：11 Pages

TI

德州仪器

36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：135.24 Kbytes 页数：9 Pages

TI

德州仪器

36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：135.24 Kbytes 页数：9 Pages

TI

德州仪器