OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions Noninverting Outputs Typical VOLP (Output Ground Bounce)

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OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：121.61 Kbytes 页数：17 Pages

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OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：578.36 Kbytes 页数：19 Pages

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OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：548.7 Kbytes 页数：19 Pages

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OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：548.7 Kbytes 页数：19 Pages

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OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：578.36 Kbytes 页数：19 Pages

TI

德州仪器

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：121.61 Kbytes 页数：17 Pages

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德州仪器

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：121.61 Kbytes 页数：17 Pages

TI

德州仪器

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

文件：121.61 Kbytes 页数：17 Pages

TI

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具有三态输出的八路总线收发器和寄存器

The 'ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKEN • State-of-the-ArtEPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation• Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions• Noninverting Outputs• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C• Latch-Up Performance Exceeds 500 mA Per JESD 17• ESD Protection ;

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