SN54ABT240数据手册TI中文资料规格书

描述 Description

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\\ inputs, and complementary OE and OE\\ inputs.
The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\\ inputs. When OE\\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\\ is high, the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

·Typical VOLP (Output Ground Bounce)    CC = 5 V, TA = 25°C
·High-Drive Outputs (–32-mA IOH, 64-mA IOL)
·Ioff Supports Partial-Power-Down Mode Operation
·Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
·ESD Protection Exceeds JESD 22 ·2000-V Human-Body Model (A114-A)
·200-V Machine Model (A115-A)