SN54107中文资料具有清零端的双路 J-K 触发器数据手册TI规格书

描述 Description

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high. The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\\ output high. The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.  

特性 Features

• Package Options Include Plastic “Small Outline\" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability