丝印：SN54173J；Package：CDIP；4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS

3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes: – Parallel Load – Do Nothing (Hold) For Application as Bus Buffer Registers Pac

文件：966.44 Kbytes 页数：19 Pages

TI

德州仪器

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

description Thess uvers, monofic, 3 bit (8 da ts hs 1 parity bi) parity pmertorschckors ua Ses 4/74 TTL cet and fore oddoven outs acon apts 0 5a option n thor cdl o owen aity plications. Daperdin on whether ern oo st bing garter chckes, th vo 00 nuts cn 5 li sh pty x DU i it Th wor enh Comin

文件：400.97 Kbytes 页数：11 Pages

TI

德州仪器

丝印：SN54180J；Package：CDIP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

description Thess uvers, monofic, 3 bit (8 da ts hs 1 parity bi) parity pmertorschckors ua Ses 4/74 TTL cet and fore oddoven outs acon apts 0 5a option n thor cdl o owen aity plications. Daperdin on whether ern oo st bing garter chckes, th vo 00 nuts cn 5 li sh pty x DU i it Th wor enh Comin

文件：400.97 Kbytes 页数：11 Pages

TI

德州仪器

丝印：SN54180J；Package：CDIP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

description Thess uvers, monofic, 3 bit (8 da ts hs 1 parity bi) parity pmertorschckors ua Ses 4/74 TTL cet and fore oddoven outs acon apts 0 5a option n thor cdl o owen aity plications. Daperdin on whether ern oo st bing garter chckes, th vo 00 nuts cn 5 li sh pty x DU i it Th wor enh Comin

文件：400.97 Kbytes 页数：11 Pages

TI

德州仪器

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

Multiplexed Inputs/Outputs Provide Improved Bit Density Four Modes of Operation: Hold (Store) ~~ Shift Left Shift Right Load Data Operates with Outputs Enabled or at High Z 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for N-Bit Word Lengths Typical Power Dissipation . . . 1

文件：777.89 Kbytes 页数：9 Pages

TI

德州仪器

50/30/100-MHz PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES

Performs BCD, Bi-Quinary, or Binary Counting Fully Programmable Fully independent Clear Input Input Clamping Diodes Simplify System Design Output QA Maintains Full Fan-out Capability In Addition to Driving Clock-2 Input

文件：666.31 Kbytes 页数：14 Pages

TI

德州仪器

SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

Counts 8-4-2-1 BCD or Binary Single Down/Up Count Control Line Count Enable Control Input Ripple Clock Output for Cascading Asynchronously Presettable with Load Control Parallel Outputs Cascadable for n-Bit Applications

文件：627 Kbytes 页数：17 Pages

TI

德州仪器

SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

Counts 8-4-2-1 BCD or Binary Single Down/Up Count Control Line Count Enable Control Input Ripple Clock Output for Cascading Asynchronously Presettable with Load Control Parallel Outputs Cascadable for n-Bit Applications

文件：627 Kbytes 页数：17 Pages

TI

德州仪器