SMJ320C6701-SP中文资料德州仪器数据手册PDF规格书

1FEATURES

23456• Rad-Tolerant: 100-kRad (Si) TID

• SEL Immune at 89MeV-cm2/mg LET Ions

• QML-V Qualified, SMD 5962-98661

• Highest-Performance Floating-Point Digital

Signal Processor (DSP) SMJ320C6701

– 7-ns Instruction Cycle Time

– 140-MHz Clock Rate

– Eight 32-Bit Instructions/Cycle

– Up to One GFLOPS Performance

– Pin Compatible With ’C6201 Fixed-Point

DSP

• SMJ: QML Processing to MIL-PRF-38535

• SM: Standard Processing

• Operating Temperature Ranges

– –55°C to 115°C

– –55°C to 125°C

• VelociTI™ Advanced Very Long Instruction

Word (VLIW) ’C67x CPU Core

– Eight Highly Independent Functional Units:

– Four ALUs (Floating and Fixed Point)

– Two ALUs (Fixed Point)

– Two Multipliers (Floating and Fixed

Point)

– Load-Store Architecture With 32

32-Bit General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

• Instruction Set Features

– Hardware Support for IEEE Single-

Precision Instructions

– Hardware Support for IEEE Double-

Precision Instructions

– Byte Addressable (8-/16-/32-Bit Data)

– 32-Bit Address Range

– 8-Bit Overflow Protection

– Saturation

– Bit-Field Extract, Set, Clear

– Bit Counting

– Normalization

• 1M-Bit On-Chip SRAM

– 512K-Bit Internal Program/Cache (16K 32-

Bit Instructions)

– 512K-Bit Dual-Access Internal Data (64K

Bytes)

• 32-Bit External Memory Interface (EMIF)

– Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

• Four-Channel Bootloading Direct Memory Access (DMA) Controller With

Auxiliary Channel

• 16-Bit Host-Port Interface (HPI)

– Access to Entire Memory Map

• Two Multichannel Buffered Serial Ports

(McBSPs)

– Direct Interface to T1/E1, MVIP, SCSA

Framers

– ST Bus Switching Compatible

– Up to 256 Channels Each

– AC97 Compatible

– Serial Peripheral Interface (SPI)

Compatible ( Motorola™)

• Two 32-Bit General-Purpose Timers

• Flexible Phase-Locked Loop (PLL) Clock

Generator

• IEEE Std 1149.1 (JTAG (1) )

Boundary Scan Compatible

• 429-Pin Ceramic Ball Grid Array (CBGA/GLP)

and Ceramic Land Grid Array (CLGA/ZMB)

Package Types

• 0.18-μm/5-Level Metal Process

– CMOS Technology

• 3.3-V I/Os, 1.9 V Internal

• Engineering Evaluation (/EM) Samples are

Available (2)