SM8212BM中文资料POCSAG Decoder For Multiframe Pagers数据手册NPC规格书

描述 Description

OVERVIEW
The SM8212B is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes.
The SM8212B supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps. The signal input stage features a built-in filter.FEATURES
- Conforms to POCSAG standard for pagers
- 512, 1200 or 2400 bps signal speed
- Multiframe compatible (each address individually
   controllable)
- 8 addresses × 4 sub-address (total of 32 addresses)
   control
- Built-in buffer memory
- Supports tone, numeric or character call messages
- Built-in input signal filter, with filter ON/OFF and 4
   selectable filter characteristics
- PLL-compatible battery saving method (BS1, BS2,
   BS3 outputs)
- BS1 (RF control main output signal) 61-step setup
   time setting
- BS3 (PLL setup signal) 61-step setup time setting
- BS2 (RF DC-level adjustment signal) before/during
   reception selectable adjustment timing
- 1-bit and 2-bit burst error auto-correction function
- 25 to 75% duty factor signal coverage
- 8 rate error detection condition settings
- 76.8 kHz system clock (crystal oscillator)
- 76.8 or 38.4 kHz clock output pin
- Built-in oscillator capacitor and feedback resistor
- 2.0 to 3.5 V operating supply voltage
- Molybdenum-gate CMOS process realizes low power
   dissipation
- 16-pin SSOP

特性 Features

- Conforms to POCSAG standard for pagers
- 512, 1200 or 2400 bps signal speed
- Multiframe compatible (each address individually
   controllable)
- 8 addresses × 4 sub-address (total of 32 addresses)
   control
- Built-in buffer memory
- Supports tone, numeric or character call messages
- Built-in input signal filter, with filter ON/OFF and 4
   selectable filter characteristics
- PLL-compatible battery saving method (BS1, BS2,
   BS3 outputs)
- BS1 (RF control main output signal) 61-step setup
   time setting
- BS3 (PLL setup signal) 61-step setup time setting
- BS2 (RF DC-level adjustment signal) before/during
   reception selectable adjustment timing
- 1-bit and 2-bit burst error auto-correction function
- 25 to 75% duty factor signal coverage
- 8 rate error detection condition settings
- 76.8 kHz system clock (crystal oscillator)
- 76.8 or 38.4 kHz clock output pin
- Built-in oscillator capacitor and feedback resistor
- 2.0 to 3.5 V operating supply voltage
- Molybdenum-gate CMOS process realizes low power
   dissipation
- 16-pin SSOP