SM5846AP中文资料NPC数据手册PDF规格书

OVERVIEW

The SM5846AP is a multi-function digital filter that incorporates 4/8 times oversampling digital audio signal reproduction, digital deemphasis, digital attenuation and soft mute functions. The I/O interface allows serial data transmission of 16/20/24/32-bit input data and 20/24-bit output data.

FEATURES

Functions

■ 8-times oversampling (interpolation)

■ Switchable 8/4 times oversampling output

■ Two master clock frequencies (refer to Clock Functions)

• 384fs/512fs (normal-speed sampling)

• 192fs/256fs (high-speed sampling)

■ Digital deemphasis

• Compatible with 32/44.1/48kHz (normal speed) and 64/88.2/96kHz (high-speed) input sampling frequencies

• ON/OFF control

■ Digital attenuator

• 128-step attenuation using linear 7-bit data setting

■ Soft muting

• 1016/fs (normal-speed sampling)

• 2032/fs (high-speed sampling)

■ Output data round-off operation (normal round-off or rectangular distribution dither round-off)

■ Selectable LR clock polarity

■ Microprocessor controllable

■ Input data format

• 2s complement, MSB first, alternating L/R serial

• 16/20/24/32-bit data selectable

■ Output data format

• 2s complement, MSB first, simultaneous L/R serial

• 20/24-bit data selectable.

■ 24-bit internal data processing

■ Jitter-free mode/synchronous mode selectable

■ Crystal oscillator circuit built-in

■ TTL-compatible outputs

■ Molybdenum-gate CMOS

Filter Construction

■ Interpolation filter (linear 3-stage FIR filter)

• Normal-speed sampling mode

1st stage (fs to 2fs) 121st order

2nd stage (2fs to 4fs) 21st order

3rd stage (4fs to 8fs) 13th order

• High-speed sampling mode

1st stage (fs to 2fs) 177th order

2nd stage (2fs to 4fs) 29th order

3rd stage (4fs to 8fs) 17th order

■ Deemphasis filter (IIR filter)

■ Arithmetic units

• 25× 24-bit parallel adder

• 32-bit accumulator

■ Overflow limiter built-in

APPLICATIONS

■ Digital audio equipment