SLG46855-A集成电路（IC）的CPLD（复杂可编程逻辑器件）规格书PDF中文资料

 Two High Speed General Purpose Analog Comparators

(ACMPxH)

 Two Low Power General Purpose Analog Comparators

(ACMPxL)

 Two Voltage References (Vref)

 Two Vref Outputs

 Fifteen Combination Function Macrocells

 Three Selectable DFF/LATCH or 2-bit LUTs

 One Selectable Programmable Pattern Generator or

2-bit LUT

 Nine Selectable DFF/LATCH or 3-bit LUTs

 One Selectable Pipe Delay or Ripple Counter, or

3-bit LUT

 One Selectable DFF/LATCH or 4-bit LUTs

 Eight Multi-Function Macrocells

 Seven Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counters

 One Selectable DFF/LATCH or 4-bit LUT + 16-bit

Delay/Counter

 Serial Communications

 I2C Protocol Interface

 Programmable Delay with Edge Detector Output

 Deglitch Filter or Edge Detector

 Three Oscillators (OSC)

 2.048 kHz Oscillator

 2.048 MHz Oscillator

 25 MHz Oscillator