SLG46620-A_V01中文资料瑞萨数据手册PDF规格书

 8-bit Successive Approximation Register Analog-to-Digital

Converter (SAR ADC)

 ADC 3-bit Programmable Gain Amplifier (PGA)

 Two Digital-to-Analog Converters (DAC)

 Six Analog Comparators (ACMP)

 Two Voltage References (Vref)

 Twenty Five Combinatorial Look Up Tables (LUTs)

 Eight 2-bit LUTs

 Sixteen 3-bit LUTs

 One 4-bit LUT

 One Combination Function Marcocells

 Pattern Generator or 4-bit LUT

 Three Digital Comparators/Pulse Width Modulators

(DCMPs /PWMs) w/ Selectable Deadband

 Ten Counters/Delays (CNT/DLY)

 Two 14-bit Delay/Counter

 One 14-bit Delay/Counter (Wake-Sleep Control)

 One 14-bit Delay/Counter/Finite State Machine

 Five 8-bit Delay/Counter

 One 8-bit Delay/Counter/Finite State Machine

 Twelve D Flip-Flops/Latches

 Two Pipe Delays – 16 stage/ 2 output

 Two Programmable Delays w/ Edge Detection

 Three Internal Oscillators

 Low-Frequency

 Ring

 RC 25 kHz and 2 MHz