SLG46536-EV中文资料瑞萨数据手册PDF规格书

特性 Features

▪ Three Analog Comparators (ACMP)

▪ Twenty-six Combination Function Macrocells

• Three Selectable DFF/LATCH or 2-bit LUTs

• One Selectable Continuous DFF/LATCH or 3-bit LUT

• Eleven Selectable DFF/LATCH or 3-bit LUTs

• One Selectable Pipe Delay or 3-bit LUT

• One Selectable Programmable Function Generator or 2-bit LUT

• Five 8-bit Delays/Counters or 3-bit LUTs

• Two 16-bit Delays/Counters or 4-bit LUTs

• Two Deglitch Filters with Edge Detectors

▪ Combinatorial Logic

• One 4-bit LUT

▪ Serial Communications

• I2C Protocol Compliant

▪ Pipe Delay – 16 Stage/3 Output (Part of

Combination Function Macrocell)

▪ Programmable Delay

▪ Two Oscillators (OSC)

• Configurable 25 kHz or 2 MHz

• 25 MHz Oscillator

▪ Power-On Reset

▪ 16x8 RAM + OTP User Memory

• User Defined Initial Values Transferred from OTP

▪ Logic and Mixed-Signal Circuits

▪ Highly Versatile Macrocells

▪ Read Back Protection (Read Lock)

▪ Power Supply

• 1.8 V (±5 %) to 5.0 V (±10 %) VDD