SL4019BD中文资料SLS数据手册PDF规格书

Quad AND/OR Select Gate

High-Voltage Silicon-Gate CMOS

The SL4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input gate. Selection is accomplished by control bits Sa and Sb .In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply