SL23EP08SC-2集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Description

The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to eight (8) clock outputs from one (1) reference input clock, for high speed clock distribution applications.

Key Features

• 10 to 220 MHz operating frequency range

• Low output clock skew: 70ps-typ

• Low output clock Jitter: 50 ps-typ

- 50 ps-typ at 166MHz, CL=15pF and VDD=3.3V

- 75 ps-typ at 166MHz, CL=15pF and VDD=2.5V

• Low part-to-part output skew: 150 ps-typ

• 3.3V to 2.5V power supply range

• Low power dissipation:

• - 22 mA-typ at 66MHz and VDD=3.3V

• - 20 mA-typ at 66MHz and VDD=2.5V

• One input drives 8 outputs

• Multiple configurations and drive options

• Select mode to bypass PLL or tri-state outputs

• SpreadThru™ PLL that allows use of SSCG

• Available in 16-pin SOIC and TSSOP packages

• Available in Commercial and Industrial grades

Benefits

• Up to eight (8) distribution of input clock

• Standard and High-Dirive levels to control impedance level, frequency range and EMI

• Low skew, jitter and power dissipation

Applications

• Printers, MFPs and Digital Copiers

• PCs and Work Stations

• Routers, Switchers and Servers

• Datacom and Telecom

• High-Speed Digital Embeded Systems