SI5396C-A-EVB中文资料思佳讯数据手册PDF规格书

KEY FEATURES

• Each DSPLL generates any output

frequency from any input frequency

• Four or two DSPLLs to synchronize to

multiple time domains

• Ultra-low phase jitter of 95 fs rms

• Enhanced hitless switching minimizes

output phase transients

• Input frequency range:

• Differential: 8 kHz to 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range:

• Differential: 100 Hz to 720 MHz

• LVCMOS: 100 Hz 250 MHz

• Status Monitoring

• Si5397: 4-PLL, 8/4 output, 64-QFN/LGA

• Si5396: 2-PLL, 4 output, 44-QFN/LGA and

12 output, 64-QFN/LGA

• External reference: Grades A/B/C/D

• Integrated reference: Grades J/K/L/M

• Drop-in compatible with Si5347/46