Si5382A数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The Si5382A is an ultra-low phase noise jitter attenuating clock multiplier optimized for wireless applications which demand the highest level of integration and phase noise performance with ultra-small form factor and power consumption. The Si5382A accepts 4 clock inputs ranging from 0.008 to 750 MHz and generates 12 clock outputs from 0.000001 to 2949.12 MHz. Based on our 4th generation DSPLL technology, the device combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Learn more about wireless DSPLL technology.

简介

Si5382A属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的Si5382A时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。