1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

文件：158.78 Kbytes 页数：20 Pages

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

文件：158.78 Kbytes 页数：20 Pages

SILABS

芯科科技

The Si5330 Clock Buffer datasheet v1.0 is now available

文件：41.28 Kbytes 页数：1 Pages

SILABS

芯科科技

Package：24-VFQFN 裸露焊盘；包装：管件 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:4 710MHZ 24QFN

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